1. Field of Invention
The present invention relates to an electrostatic discharge protection circuit for an integrated circuit. More particularly, the present invention relates to a gate-driven and substrate-triggered electrostatic discharge protection circuit.
2. Description of Related Art
In general, an electrostatic discharge (ESD) through an integrated circuit IC may damage some of the internal semiconductor devices that the IC is no longer functional. ESD often produces a large current within a short transient interval that loading capacity of the semiconductor devices is exceeded.
To prevent damages to the IC, an on-chip ESD protection circuit is generally incorporated into an IC chip. The ESD protection circuit can be regarded as a type of switch that turns on when an ESD incidence is triggered by a voltage surge. The ESD current caused by the voltage surge is discharged through an alternative route instead of passing through the IC circuit. However, without any unusual voltage surge, the ESD protection circuit remains off so that normal operation of the IC circuit is unaffected.
The incorporation of an ESD protection circuit into a deep-submicron CMOS circuit is particularly difficult because the gate oxide layer is relatively thin in deep submicron fabrication. In addition, breakdown voltage of the gate oxide layer is relatively low, about 10V. Therefore, triggering voltage of the ESD protection circuit must be lowered to a level below the breakdown voltage of the gate oxide layer in order to provide an effective protection. In the following, a few conventional ESD protection circuits are introduced.
FIG. 1 is a first conventional ESD protection circuit disclosed in U.S. Pat. No. 5,910,874. The circuit has a gate-to-ground connecting configuration. As shown in FIG. 1, the gate terminal and the source terminal of a transistor M1 are both connected to a ground terminal. The drain terminal of the transistor M1 is connected to an input/output pad. This circuit utilizes junction avalanche breakdown of the transistor M1 to bypass any ESD current. The main disadvantage of this arrangement is that the avalanche breakdown voltage and the gate oxide layer breakdown voltage are very close and hence the gate oxide layer may be easily damaged.
FIG. 2 is a second conventional ESD protection circuit disclosed in U.S. Pat. No. 5,646,808. The circuit includes a pair of transistors 12 and 14. The drain terminal of the transistor 12 is connected to an input/output pad 16 and the gate terminal of the transistor 12 is connected to the drain terminal and the gate terminal of the transistor 14. The source terminals of transistors 12 and 14 are connected to a ground terminal. The gate control circuit (transistor 14) triggers the transistor 12 directly into a snapback region so that the triggering voltage is lower than a normal value. The main disadvantage of this invention is that the triggering voltage rises without falling if the voltage coupled to the gate of the transistor 12 having a certain high value. FIG. 3 is a graph showing the characteristic drain current ID versus drain voltage VD under various gate-to-source voltages VGS.
FIG. 4 is a conventional gate-driven ESD protection circuit disclosed by U.S. Pat. No. 5,519,242. The gate control circuit includes a Zener diode 22 and a resistor 26. The cathode of the Zener diode is connected to a point along the conductive line joining the drain terminal D of an NMOS transistor 24 and a voltage source as well as an input/output pad. The anode of the Zener diode is connected to a point along the conductive line joining the gate terminal G of the NMOS transistor 24 and one end of the resistor 26. The other end of the resistor 26 is connected to the source terminal S of the transistor 24 as well as a voltage source VSS.
FIG. 5 is a conventional capacitor-coupled ESD protection circuit disclosed by U.S. Pat. No. 5,631,793. The circuit is inserted between an input pad 31 and an internal circuit 33. The circuit also has ESD bypass devices 323, 324 for carrying ESD current. The capacitor-coupled circuit is used for coupling a portion of the voltage to the ESD clamping device 323. By optimizing resistor parameters (Rp, Rn) 321 and capacitor parameters (Cp1, Cp2) 322, snapback breakdown voltage can be greatly lowered such that the thin gate oxide layer is well protected.
FIG. 6 is a conventional gate-body-coupled ESD protection circuit disclosed by U.S. Pat. No. 5,811,857. The main body (substrate) 428 and the gate terminal 422 of the MOSFET transistor are connected together to form a dynamic threshold voltage MOSFET device 42. The gate terminal of the device 42 is connected to a level shifting device 44. When voltage applied to the gate terminal 422 of the MOSFET and the main body 428 rises, threshold voltage of the MOSFET decreases correspondingly.
Accordingly, one object of the present invention is to provide a double-triggered electrostatic discharge (ESD) protection circuit. The circuit can be substrate-triggered and gate-driven so that the triggering voltage level is reduced and protection capacity provided by the ESD protection circuit is enhanced.
A second object of this invention is to provide a double-triggered ESD protection circuit. The ESD protection circuit is incorporated into a circuit chip for dealing with any static electricity buildup between an input/output pad and a voltage source (VDD or VSS).
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a double-triggered electrostatic discharge (ESD) protection circuit. The ESD protection circuit couples with a first voltage source and a second voltage source and includes a diode series and a transistor. The diode series comprises a plurality of serially connected diodes with the cathode of one diode connected to the anode of a subsequent diode. The positive terminal of the first diode in the diode series connects with the first voltage source. The gate terminal of the transistor connects with the anode of the last diode in the diode series. The substrate of the transistor connects with the cathode of the last diode in the diode series. The source terminal and the drain terminal of the transistor connect with the first voltage source and the second voltage source, respectively.
This invention also provides a second double-triggered electrostatic discharge (ESD) circuit coupled to an input/output pad, a voltage source (for example, for providing a relatively low voltage VSS to the circuit) and an internal circuit. The double-triggered ESD circuit includes a diode, a diode series and a transistor. The cathode of the diode is connected to the input/output pad and the anode is connected to the voltage source. The diode series comprises a plurality of serially connected diodes. The positive terminal of the first diode in the diode series is connected to the input/output pad. The gate terminal of the transistor is connected to the anode of the last diode of the diode series. The substrate of the transistor is connected to the cathode of the last diode in the diode series. The source terminal and the drain terminal of the transistor are connected to the input/output pad and the voltage source, respectively.
This invention also provides a third double-triggered electrostatic discharge (ESD) circuit coupled to an input/output pad, a voltage source (for example, for providing a relatively high voltage VDD to the circuit) and an internal circuit. The double-triggered ESD circuit includes a diode, a diode series and a transistor. The anode of the diode is connected to the input/output pad and the cathode is connected to the voltage source. The diode series comprises a plurality of serially connected diodes. The anode of the last diode of the diode series is connected to the input/output pad. The gate terminal of the transistor is connected to the anode of the first diode in the diode series. The substrate of the transistor is connected to the cathode of the first diode in the diode series. The source terminal and the drain terminal of the transistor are connected to the input/output pad and the voltage source, respectively.
This invention also provides a fourth double-triggered electrostatic discharge (ESD) circuit coupled to an input/output pad, a first voltage source (for example, for providing a relatively high voltage VDD to the circuit) and a second voltage source (for example, for providing a relatively low voltage VSS to the circuit). The double-triggered ESD circuit includes a first diode, a first diode series, a first transistor, a second diode, a second diode series, a second transistor, a third diode series and a third transistor. The anode of the first diode is connected to the input/output pad and the cathode of the first diode is connected to the first voltage source. The first diode series comprises a plurality of serially connected diodes. The cathode of the last diode in the first diode series is connected to the input/output pad. The gate terminal of the first transistor is connected to the cathode of the first diode in the first diode series. The substrate of the first transistor is connected to the anode of the first diode in the first diode series. The source terminal and the drain terminal of the first transistor are connected to the input/output terminal and the first voltage source, respectively. The cathode of the second diode is connected to the input/output pad and the anode of the second diode is connected to the second voltage source. The second diode series comprises a plurality of serially connected diodes. The anode of the first diode in the second diode series is connected to the input/output pad. The gate terminal of the second transistor is connected to the anode of the last diode in the second diode series. The substrate of the second transistor is connected to the cathode of the last diode in the second diode series. The source terminal and the drain terminal of the second transistor are connected to the input/output pad and the second voltage source, respectively. The third diode series comprises a plurality of serially connected diodes. The anode of the first diode in the third diode series is connected to the first voltage source. The gate terminal of the third transistor is connected to the anode of the last diode in the third diode series. The substrate of the third transistor is connected to the cathode of the last diode in the third diode series. The source terminal and the drain terminal of the third transistor are connected to the first and the second voltage source, respectively.
The aforementioned double-triggered ESD protection circuit is substrate-triggered as well as gate-triggered so that the triggering voltage is lowered and protective capacity of the ESD protection circuit is enhanced. In the meantime, the protection circuit can be easily incorporated into a circuit chip to deal with any static electricity buildup between an input/output pad and respective power sources VDD and VSS.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.